Amplifier



J Dec. 4, 1951 BELLEWLLE 2,577,506

AMPLIFIER Filed July 9, 1945 OUT OUT

IN VEN TOR.

LOGAN MBELLEV/LLE' BY Patented Dec. 4, 1951 UNITED STATES PATENT OFFICE ANIPLIFIER Logan M.;1 3e lle,ville, Watertown, -Mass., assignor, by mesne assignments -to the .United States of America. as represented by the, Secretaryof War Application July 9, 1945,-Serial No. 604,035

.7 Claims. 1

The present invention relates in general to electronic circuits and more specifically to an electronic network'whose output voltage is proportional tothe logarithm of its input voltage.

In some applications of electronic apparatus, it is highly desirable .to facilitate operation'by providing an electronic network whose output does-not vary linearly withthe input voltage, but rather asthe, logarithm-of the input voltage. One of theobjectsof the present invention, therefore, is .to provide anelectronicnetwork whose. operating characteristicssatisfy this requirement.

For some types of cathode ray apparatus numerous advantages are obtained by utilizing a logarithmic output for accomplishing particular types of scanning. Accordingly, it is another object of-my invention to provide circuits for transforming an input signal into an output signal Whosevalue issubstantially proportional to the logarithm of the input signal, so that it may be utilized in connection with cathode-ray oscilloscopes with someinherent advantages obtained due to such transformation.

In general my invention contemplates dividing or transforming an input vol-tageunto aseries of voltages bearing -a predetermined relationship with respect to each other, and utilizing each of these voltages to control thermionic apparatus to obtain an output logarithmically'related with respect to the input voltage. The logarithmic output signal is obtained by combining at least a portion of the outputs of the controlled thermionic apparatus in a common outputcircuit.

For a better understanding of the invention, together with other and further objects thereof, reference is had to the following description taken in connection with the accompanying drawings, in which:

Fig. 1 is one embodiment of my invention; and

Fig. 2 is a schematic diagram illustratinga block diagram an alternate form of my. invention.

Referring now .more particularly 151 111g. ,1, serially connected resistances l0, l2, and I4, which by way of example may be in the ,ratio of 100:10z1, make up a voltage divider or a potentiometer across which-the total-input voltage is'applied through capacitor I6. The total input voltage is also applied to the grid or vacuum tube l8 whose input circuit is thus connected ,aCIQSs theentirepotentiometer. Th v lta aatthe te minal-point between resisto la d 2. applied totthe grid :of tube :20 and swan b :see 1793 the values .;of the resistors in the:,exampl e shown, this :amounts 1-to; about,oneten th ;of the input voltage. The :voltage at the terminal point be.- tween-resistors l 2 and I4 is applied to the grid of vacuum ,tube "22, and in the same examplethis can-be seen to be approximately one-hundredth of thetotalinput voltage. Tubes I8, 20, and 22 have acommon load resistor 24, across which the outputs of the tubes are combined simultaneously, the total output voltage being a result of the sum of the three tube currents flowing through resistor;24.

Describing now 'the operation of the system of Fig. 1, an input signal is received ,andattenuated by .the voltage divider as previously explained. Thus if tube It receives a volt signal, tubelll receives 1 volt, and tube 22 receivesJA volt. The tubes are so chosen that they will saturate at some predetermined point, and only when a tube saturates does the output of the tube receiving the next smaller input become significant. For example, suppose tube I8 saturates when the input :is lsvolt. Then, assuming the amplification of each stage to be 10, the output will be approximately 10volts. In order to saturate tube 20, the input voltage must be 10 volts, if the tubes are identical, due to thestep-down ratio of the voltage divider. At this time the output will be volts, the sum of the maximum outputs of tubes 18 and 2|]. The output from tube 22 at this time is still negligible. Similarly, the-input voltage :must .reach 100 volts before tube 22 saturates, andithe outputthen would be volts, the sum of the maximum outputs of the three tubes. Thus we'havean output proportional to the logarithm of the input, and, as can beseen, the baseof-;.the-logarithm is cleterminediby the ratio of the elements of the voltage divider.

Referringnext to Fig. 2, we have a block diagramof a portion of a radio receiving system employinga slightly different form of theinvention. The 1.;F. input is fed through twoconventional I. F. amplification stages, 26 and 2 8-to Q S ECQIIdySGIiQS'Qf serially connected I. F. amplifi rs 2 and .4 .Th mu an o am l fier 3 0 is-;f edr-to,-a,detector 36,,as well as to the .succeeding I. ,F. stage, and the output of amplifier 3zris dividedin1 the same-way,'being ied both to detector fill-and I. Foamplifier 34. The output of amplifierfi 'r. goes-toe. detector 40. If we so choose, the last three 1'. F. stages may each have, by way of example-an amplification .of -10; thus, t-ca h s entha the l ,9 m his case the e ui a en 1 th rolta i e .F.

the three1I-. eu au volt se zeineagain-l h ratio of 1.0,0 l0 1. The outputs of the three deeeter h o e d v l ps .three orr s ondin signal voltages in the ratio 100:10:1 which are fed to three separate video amplifiers 42, 44, and 46, the outputs of which are combined through a common load resistor 48 in the same manner as in the apparatus of Fig. 1. By analogous performance the output signal of this receiver will be proportional to the logarithm of the amplitude of I. F. input and the base of the logarithm system will be determined by the gain of these last three I. F. stages.

It will be noted that in the Fig. 2 arrangement and example a small signal output from I. F. amplifier 28 is multiplied by a factor in each of the successive stages 30, 32 and 34 to provide a corresponding plurality of inputs, to detectors 36, 38 and 49. In the arrangement and example of Fig. l a large signal which is applied across the series connected impedances l0, l2 and I4 is divided by a factor of 10 to provide a correspond-' ing plurality of inputs to the grids of amplifier tubes I8, 29 and 22. It is evident that the inputs to amplifiers I8, 28 and 22 of Fig. 1 respectively correspond to the inputs to detectors 4!], 3B and 36 of Fig. 2. In both examples the arrangement is adapted to provide a plurality of similar signals at a corresponding plurality of terminals, the values of said signals being related substantially in geometric progressive order, the ratio of the amplitudes of successive signals in the progression having a chosen value corresponding to a desired logarithmic base which in both examples was taken as 10.

In both arrangements and examples a corresponding plurality of translating devices are operatively connected with said terminals, each of said devices having similar characteristics and adapted to repeat the signal amplitudes between predetermined amplitude levels. In both arrangements there is a common output circuit for the device.

It will be obvious that the examples given in Fig. 1 and Fig. 2 are illustrative only, and that many other variations, including changes in number and magnitude of circuit elements, are possible while remaining within the scope of the invention.

The invention thus discloses an electrical circuit for transforming an input signal into an output signal which is substantially proportional to the logarithm of the input signal, the circuit including any suitable electrical means, such as a potentiometer illustrated in Fig. 1 or a plurality of cascade-connected amplifiers illustrated in Fig. 2, for transforming the input signal into a plurality of signals whose respective values are proportional to a geometric progression, and a corresponding plurality of saturable electrical networks having their input circuits connected to the respective terminals of said means. These networks, in Fig. 1, correspond to the parallellyconnected amplifiers I8, 20, and 22, while in Fig. 2 they correspond to the detectors 36, 38, and 40 and video amplifiers 42, 44, and 46. These networks reach successive current saturations at a common voltage with respect to ground, since the cathodes of the amplifiers, such as amplifiers I8, 20, and 22, are normally connected to ground. The same is true of the detectors 36, 38, and 40 in Fig. 2. However, the conductivity of these amplifiers is varied in response to any increase in the input voltage across the previously mentioned input means, which is obtained by proportioning the impedances, such as resistances ID, l2, and [4 in Fig. l or the gains of the amplifiers 30, 32, and 34 in Fig. 2, so that the input signal is transformed into a plurality of signals having geometric progression relationship with respect to each other. The logarithm output is then obtained by combining the output of the parallel paths in one, common output circuit for all the networks.

While there have been described two embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention, and it is, therefore, aimed in the appended claims to cover all such changes and modifications as fall within the true spirit and scope of the invention.

What I claim is:

1. An electrical circuit for transforming an input signal into an output signal substantially proportional to the logarithm of said input signal comprising a source of said input signal, means connected to said source and having a plurality of terminals, said means producing, at said terminals, a corresponding plurality of successively smaller signals whose respective values are substantially proportional to a geometric progression having a quotient which is less than unity, said producing means comprising signal translating elements connected in an operative series, the translation of the signal by each of said elements being dependent upon the translation by the respective preceding'element; a corresponding plurality of saturable electrical networks having their input circuits connected to the respective terminals of said means, said networks reaching successive current saturations at a common voltage with respect to ground but in response to an increase in the input voltage across said means in the manner of geometric progression, and a common load circuit in parallel with the output circuits of all of said networks.

2. An electrical circuit for transforming an input signal into an output signal substantially proportional to the logarithm of said input signal comprising means for transforming said input signal into a plurality of successively smaller signals whose values are substantially proportional to a geometric progression having a quotient which is less than unity at a corresponding plurality of terminals on said means, said transforming means comprising signal translating elements connected in an operative series, the translation of the signal by each of said elements being dependent upon the translation by the respective preceding element; a corresponding plurality of saturable electrical networks having their input circuits connected to the respective terminals of said means, said networks reaching respective successive saturations at a common voltage with respect to a common point of reference potential on said means in response to an increase of said input signal when the input voltage is increased in the manner of said geometric progression, and a common load circuit in parallel with the output circuits of all of said netrespect to a common point of reference potential on said potentiometer and in response to an increase in said input signal, the input circuit of one amplifier being connected across said potentiometer, and the inputs of the remaining amplifiers being connected respectively to the remaining successive terminals of said potentiometer, and a common output circuit interconnecting all of said amplifiers.

4. A receiver comprising a plurality of cascade-connected intermediate frequency amplifiers whose respective output voltages are substantially proportional to a geometric progression, a plurality of parallelly connected detectors, the number of said detectors being equal to the number of said intermediate-frequency amplifiers, the respective input circuits of said detectors being connected to the corresponding outputs of said intermediate-frequency amplifiers, a plurality of video amplifiers, the number of said video amplifiers being equal to the number of said detectors, the respective input circults of said video amplifiers being connected to the corresponding output circuits of said detectors, whereby said intermediate-frequency amplifiers, detectors, and video amplifiers form a plurality of parallelly connected channels, and a common load circuit in parallel with the output circuits of all of said video amplifiers.

'5. An electrical circuit for transforming an input circuit signal into an output signal substantially proportional to the logarithm of the amplitude of said input signal to a chosen base com prising means for transforming said input signal into a plurality of similar signals at a corresponding plurality of terminals, said transforming means being comprised of a plurality of cascade operable elements, one disposed between corresponding ones of said terminals, said similar signals having amplitudes which are related substantially in a geometric progressive order having a quotient less than unity, the ratio of the amplitudes of successive signals in the progression and the operative characteristics of said elements having a chosen value corresponding to a desired logarithmic base, a corresponding plurality of translating devices saturable at a common voltage with respect to a common point of reference potential on said means and in response to an increase of said input signal and operatively connected with said terminals to repeat said signals between predetermined amplitude levels and a common load circuit in parallel with the output circuits ofall said devices.

6. An electrical circuit for transforming an input signal into an output signal substantially proportional to the logarithm of the amplitude of said input signal to a chosen base comprising a potentiometer signal dividing means for transforming said input signal into a plurality of similar signals at a corresponding plurality of terminals, said potentiometer having portions and said similar signals having amplitudes which are related substantially in a geometric progressive order having a quotient which is less than unity. the ratio of the potentiometer portions and of the amplitudes of successive signals in the progression having a chosen value corresponding to a desired logarithmic base, a corresponding plurality of electronic translating devices having in-. put elements operatively connected with said terminals to repeat said signals similarly between predetermined amplitude levels being saturable at a common voltage with respect to a common point of reference potential on said potentiometer and in response to an increase of said input signal, and a common output circuit for all said devices.

7. An electrical circuit for transforming a modulated carrier wave input signal into an output signal substantially proportional to the logarithm of the modulation amplitude of said input signal to a chosen base comprising amplifier means having a plurality of subsidiary cascade-connected operative subsidiary portions for transforming said input signal into a plurality of similar signals at a corresponding plurality of terminals, said portions having operative characteristics and said similar signals having amplitudes which are related substantially in a geometric progressive order having a quotient which is less than unity, the operative ratio of said portions and the ratio of the values of successive signals in the progression having a chosen value corresponding to a desired logarithmic base, a corresponding plurality of translating devices operatively connected with said terminals to detect the modulation of said similar signals and to repeat said modulation between predetermined amplitude levels being saturable at a cormnon voltage with respect to a common point of reference potential on said transforming means and in response to an increase of'said input signal and a common load circuit in parallel with the output circuits of all said devices.

LOGAN M. BELLEVILLE.

REFERENCES CITED The following references are of record in the file of this patent:

UNITED STATES PATENTS McGraw-Hill, 1943, page 622. 

